Exemplary embodiments relate to a voltage generation circuit and a nonvolatile memory device including the same, which are capable of compensating for the bouncing phenomenon of a global source line.
There is an increasing demand for semiconductor memory devices which can be electrically programmed and erased and can retain data without being supplied with power. In order to develop high-capacity memory devices capable of storing a large amount of data, technology for the high integration of memory cells is being developed.
To this end, a nonvolatile memory device may include a number of cell strings. Each of the cell strings includes a number of memory cells coupled in series together.
Recently, to further increase the degree of integration of nonvolatile memory devices, active research is being done on a multi-bit cell which is able to store plural bits of data in a single memory cell. This type of a memory cell is called a multi-level cell (MLC). A memory cell capable of storing one bit is called a single level cell (SLC).
FIG. 1 is a diagram schematically showing an example in which the memory cells of a conventional nonvolatile memory device are coupled together.
Referring to FIG. 1, the nonvolatile memory device 100 includes a memory cell array 110, a page buffer unit 120, and an X decoder 130.
The memory cell array 110 includes memory blocks each comprising a number of cell strings ST0, ST1 . . . STm.
Each of the cell strings includes a number of memory cells coupled in series between a drain select transistor DST and a source select transistor SST. Word lines WL0 . . . WL31 are respectively coupled to the gates of the memory cells.
A drain selection line DSL is coupled to the gates of the drain select transistors DST, and a source selection line SSL is coupled to the gates of the source select transistors SST.
A bit line is coupled to the drain of the drain select transistor DST of each cell string. An even bit line BLe and an odd bit line BLo form a pair and each pair is coupled with one page buffer PB.
Furthermore, the source of the source select transistor SST of each cell string is coupled to a global source line SL.
The page buffer unit 120 includes a number of page buffers PB. Each page buffer PB is configured to latch data to be stored in a memory cell coupled to a selected bit line. The page buffers PB are also configured to store data read from a memory cell.
The X decoder 130 is configured to select the word lines, the drain selection line, and the source selection line when a program, verification, read, or erase operation is performed.
To perform the read operation or the verification operation, the nonvolatile memory device 100 first precharges a selected bit line through a corresponding page buffer PB.
Next, the nonvolatile memory device 100 supplies a selected word line with a read voltage or a verification voltage, and the remaining word lines with a pass voltage. Such an operation is called an evaluation process. According to the evaluation process, voltage of the selected bit line remains in a precharge state or it is discharged according to the state of data stored in a memory cell coupled to the selected word line.
Next, a changed voltage of the bit line is sensed, and a result of the sensing is latched in the page buffer PB.
During the evaluation process, the global source line SL is coupled to a ground node.
If the selected memory cell is in a program state, the voltage of the bit line remains in a precharge state. However, if the selected memory cell is not in a program state, the voltage of the bit line is discharged toward the global source line SL via a corresponding cell string.
The term ‘program state’ refers to a state in which the threshold voltage of a memory cell is higher than a read voltage or a verification voltage applied to the gate of the memory cell. The term ‘erase state’ refers to a state in which the threshold voltage of a memory cell is lower than a read voltage or a verification voltage applied to the gate of the memory cell.
Thus, in the program state, a memory cell is in a turn-off state, and in the erase state, a memory cell is in a turn-on state.
During the read operation or the verification operation, the voltage of a bit line may not be sufficiently discharged because of the resistance component of the global source line commonly coupled to the cell strings.
That is, the global source line must maintain a ground voltage level. However, the global source line has a bouncing resistor Rs. So, the global source line may not maintain 0 V, and instead, the voltage level may bounce because of an electric current flowing therethrough. If a bouncing phenomenon occurs in the global source line, the source line maintains a voltage more than 0 V during the evaluation process. Further, if the source line has a voltage more than 0 V, the voltage of a bit line may not be sufficiently discharged during the evaluation time when data of an erased cell are read.